 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features * 1.65V - 1.95V Read/Write * High Performance - Random Access Time - 70 ns - Page Mode Read Time - 20 ns - Synchronous Burst Frequency - 66 MHz - Configurable Burst Operation Sector Erase Architecture - Eight 4K Word Sectors with Individual Write Lockout - One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout Typical Sector Erase Time: 32K Word Sectors - 700 ms; 4K Word Sectors - 200 ms Four Plane Organization, Permitting Concurrent Read in Any of the Three Planes not Being Programmed/Erased - Memory Plane A: 25% of Memory Including Eight 4K Word Sectors - Memory Plane B: 25% of Memory Consisting of 32K Word Sectors - Memory Plane C: 25% of Memory Consisting of 32K Word Sectors - Memory Plane D: 25% of Memory Consisting of 32K Word Sectors Suspend/Resume Feature for Erase and Program - Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 30 mA Active - 35 A Standby VPP Pin for Write Protection and Accelerated Program Operations RESET Input for Device Initialization CBGA Package Top or Bottom Boot Block Configuration Available 128-bit Protection Register Common Flash Interface (CFI) * * * * 64-megabit (4M x 16) Burst/Page Mode 1.8-volt Flash Memory AT49SN6416 AT49SN6416T * * * * * * * 1. Description The AT49SN6416(T) is a 1.8-volt 64-megabit Flash memory. The memory is divided into multiple sectors and planes for erase operations. The device can be read or reprogrammed off a single 1.8V power supply, making it ideally suited for In-System programming. The device can be configured to operate in the asynchronous/page read (default mode) or burst read mode. The burst read mode is used to achieve a faster data rate than is possible in the asynchronous/page read mode. If the AVD and the CLK signals are both tied to GND and the burst configuration register is configured to perform asynchronous reads, the device will behave like a standard asynchronous Flash memory. In the page mode, the AVD signal can be tied to GND or can be pulsed low to latch the page address. In both cases the CLK can be tied to GND. The AT49SN6416(T) is divided into four memory planes. A read operation can occur in any of the three planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of 3464C-FLASH-2/05 time and let the user read data from or program data to any of the remaining sectors. There is no reason to suspend the erase or program operation if the data to be read is in another memory plane. The VPP pin provides data protection and faster programming times. When the V PP input is below 0.4V, the program and erase functions are inhibited. When VPP is at 0.9V or above, normal program and erase operations can be performed. With VPP at 10.0V, the program (Dualword Program command) operation is accelerated. 2. Pin Configurations Pin Name I/O0 - I/O15 A0 - A21 CE OE WE AVD CLK RESET WP VPP WAIT VCCQ NC Pin Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Address Latch Enable Clock Reset Write Protect Write Protection and Power Supply for Accelerated Program Operations WAIT Output Power Supply No Connect 2.1 56-ball CBGA (Top View) 1 2 3 4 5 6 7 8 A B C D E F G A11 A12 A8 VSS VCC VPP A18 A9 A20 CLK RESET A17 A6 A5 A7 NC A4 A3 A2 A1 A0 A13 A10 A21 AVD WE A19 A15 A14 WAIT A16 I/O12 WP VCCQ I/O15 I/O6 I/O4 I/O2 I/O1 CE VSS I/O14 I/013 I/O11 I/O10 I/O9 I/O0 OE I/O7 VSS I/O5 VCC I/O3 VCCQ I/O8 VSS 2 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 3. Device Operation 3.1 Command Sequences When the device is first powered on, it will be in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. Prior to the low-going pulse on the CE or WE signal, the address input may be latched by a low-to-high transition on the AVD signal. If the AVD is not pulsed low, the address will be latched on the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences. 3.2 Burst Configuration Command The Program Burst Configuration Register command is used to program the burst configuration register. The burst configuration register determines several parameters that control the read operation of the device. Bit B15 determines whether synchronous burst reads are enabled or asynchronous reads are enabled. Since the page read operation is an asynchronous operation, bit B15 must be set for asynchronous reads to enable the page read feature. The rest of the bits in the burst configuration register are used only for the burst read mode. Bits B13 - B11 of the burst configuration register determine the clock latency for the burst mode. The latency can be set to two, three, four, five or six cycles. The "Clock Latency versus Input Clock Frequency" table is shown on page 21. The "Burst Read Waveform" as shown on page 32 illustrates a clock latency of four; the data is output from the device four clock cycles after the first valid clock edge following the high-to-low AVD edge. The B10 bit of the configuration register determines the polarity of the WAIT signal. The B9 bit of the burst configuration register determines the number of clocks that data will be held valid (see Figure 8-1). The Hold Data for 2 Clock Cycles Read Waveform is shown on page 32. The clock latency is not affected by the value of the B9 bit. The B8 bit of the burst configuration register determines when the WAIT signal will be asserted. When synchronous burst reads are enabled, a linear burst sequence is selected by setting bit B7. Bit B6 selects whether the burst starts and the data output will be relative to the falling edge or the rising edge of the clock. Bits B2 - B0 of the burst configuration register determine whether a continuous or fixed-length burst will be used and also determine whether a four-, eight- or sixteen-word length will be used in the fixed-length mode. All other bits in the burst configuration register should be programmed as shown on page 21. The default state (after power-up or reset) of the burst configuration register is also shown on page 21. 3 3464C-FLASH-2/05 3.3 Asynchronous Read There are two types of asynchronous reads - AVD pulsed and standard asynchronous reads. The AVD pulsed read operation of the device is controlled by CE, OE, and AVD inputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. The data at the address location defined by A0 - A21 and captured by the AVD signal will be read when CE and OE are low. The address location passes into the device when CE and AVD are low; the address is latched on the low-tohigh transition of AVD. Low input levels on the OE and CE pins allow the data to be driven out of the device. The access time is measured from stable address, falling edge of AVD or falling edge of CE, whichever occurs last. During the AVD pulsed read, the CLK signal may be static high or static low. For standard asynchronous reads, the AVD and CLK signal should be tied to GND. The asynchronous read diagrams are shown on page 29. 3.4 Page Read The page read operation of the device is controlled by CE, OE, and AVD inputs. The CLK input is ignored during a page read operation and should be tied to GND. The page size is four words. During a page read, the AVD signal can transition low and then transition high, transition low and remain low, or can be tied to GND. If a high to low transition on the AVD signal occurs, as shown in Page Read Cycle Waveform 1, the page address is latched by the low-to-high transition of the AVD signal. However, if the AVD signal remains low after the high-to-low transition or if the AVD signal is tied to GND, as shown in Page Read Cycle Waveform 2, then the page address (determined by A21 - A2) cannot change during a page read operation. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page being output at a speed of 20 ns. If the AVD and the CLK pins are both tied to GND, the device will behave like a standard asynchronous Flash memory. The page read diagrams are shown on page 30. 3.5 Synchronous Reads Synchronous reads are used to achieve a faster data rate than is possible in the asynchronous/page read mode. The device can be configured for continuous or fixed-length burst access. The burst read operation of the device is controlled by CE, OE, CLK and AVD inputs. The initial read location is determined as for the AVD pulsed asynchronous read operation; it can be any memory location in the device. In the burst access, the address is latched on the first valid clock edge when AVD is low or the rising edge of the AVD signal, whichever occurs first. The CLK input signal controls the flow of data from the device for a burst operation. After the clock latency cycles, the data at the next burst address location is read for each following clock cycle. Figure 3-1. Word Boundary Word D0 - D3 D0 D1 D2 Word D4 - D7 D5 D6 D7 Word D8 - D11 Word D12 - D15 D3 D4 D8 D9 D10 D11 D12 D13 D14 D15 4-word Boundary 16-word Boundary 4 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 3.6 Continuous Burst Read During a continuous burst read, any number of addresses can be read from the memory. When operating in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence crosses the first 16-word boundary in the memory (see Figure 3-1). If the starting address is aligned with a 4-word boundary (D0, D4, D8 or D12), there is no delay. If the starting address is not aligned with a 4-word boundary, an output delay is incurred. The delay depends on the starting address (see Table 3-1). The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated when the CE or OE signal is high. Table 3-1. Output Delay Output Delay Hold Data for 1 Clock Cycle, B9 = 0 1 Clock Cycle 2 Clock Cycles 3 Clock Cycles Output Delay Hold Data for 2 Clock Cycles, B9 = 1 2 Clock Cycle 4 Clock Cycles 6 Clock Cycles Starting Address D1, D5, D9, D13 D2, D6, D10, D14 D3, D7, D11, D15 In the "Burst Read Waveform" as shown on page 32, the valid address is latched at point A. For the specified clock latency of four, data D11 is valid within 13 ns of clock edge B. The low-to-high transition of the clock at point C results in D12 being read. The transition of the clock at point D results in a burst read of D15. The clock transition at point E does not cause new data to appear on the output lines because the WAIT signal goes low (B10 and B8 = 0) after the clock transition, which signifies that the first boundary in the memory has been crossed and that new data is not available. The clock transition at point F does cause a burst read of data D16 because the WAIT signal goes high (B10 and B8 = 0) after the clock transition indicating that new data is available. Additional clock transitions, like at point G, will continue to result in burst reads. 3.7 Fixed-length Burst Reads During a fixed-length burst mode read, four, eight or sixteen words of data may be burst from the device, depending upon the configuration. The device supports a linear burst mode. The burst sequence is shown on page 22. When operating in the linear burst read mode (B7 = 1) with the burst wrap bit (B3 = 1) set, the device may incur an output delay when the burst sequence crosses the first 16-word boundary in the memory. If the starting address is aligned with a 4-word boundary (D0, D4, D8 or D12), there is no delay. If the starting address is not aligned with a 4-word boundary an output delay is incurred. The delay depends on the starting address (see Table 3-1). The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. To indicate that the device is not ready to continue the burst, the device will drive the WAIT pin low (B10 and B8 = 0) during the clock cycles in which new data is not being presented. Once the WAIT pin is driven high (B10 and B8 = 0), the current data will be valid. The WAIT signal will be tri-stated when the CE or OE signal is high. The "Four-word Burst Read Waveform" on page 33 illustrates a fixed-length burst cycle. The valid address is latched at point A. For the specified clock latency of four, data D0 is valid within 13 ns of clock edge B. The low-to-high transition of the clock at point C results in D1 being read. Similarly, D2 and D3 are output following the next two clock cycles. Returning CE high ends the read cycle. There is no output delay in the burst access wrap mode (B3 = 0). 5 3464C-FLASH-2/05 3.8 Burst Suspend The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation if the system needs to use the Flash address and data bus for other purposes. Burst accesses can be suspended during the initial latency (before data is received) or after the device has output data. When a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. Burst Suspend occurs when CE is asserted, the current address has been latched (either rising edge of AVD or valid CLK edge), CLK is halted, and OE is deasserted. The CLK can be halted when it is at VIH or VIL. To resume the burst access, OE is reasserted and the CLK is restarted. Subsequent CLK edges resume the burst sequence where it left off. Within the device, OE gates the WAIT signal. Therefore, during Burst Suspend the WAIT signal reverts to a high-impedance state when OE is deasserted. See "Burst Suspend Waveform" on page 33. 3.9 Reset A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read mode. 3.10 Erase Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical "1". The entire memory can be erased by using the Chip Erase command or individual planes can be erased by using the Plane Erase command or individual sectors can be erased by using the Sector Erase command. 3.10.1 Chip Erase Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset during chip erase will stop the erase, but the data will be of an unknown state. 3.10.2 Plane Erase As an alternative to a full Chip Erase, the device is organized into four planes that can be individually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address is valid at the second rising edge of WE will be erased. The Plane Erase command does not alter the data in the protected sectors. 3.10.3 Sector Erase The device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second rising edge of WE will be erased provided the given sector has not been protected. 6 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 3.11 Word Programming The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a two-bus cycle operation. The programming address and data are latched in the second cycle. The device will automatically generate the required internal programming pulses. Please note that a "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. 3.12 Flexible Sector Protection The AT49SN6416(T) offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled. 3.12.1 Softlock and Unlock The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the selected sector. Hardlock and Write Protect (WP) The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden. * When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. * When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. To disable the Hardlock sector protection mode, the chip must be either reset or power cycled. 3.12.2 7 3464C-FLASH-2/05 Table 3-2. Hardlock and Softlock Protection Configurations in Conjunction with WP Hardlock 0 0 Softlock 0 1 Erase/ Prog Allowed? Yes No VPP VCC VCC WP 0 0 Comments No sector is locked Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is enabled. The sector cannot be unlocked. No sector is locked. Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is overridden and the sector is not locked. Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. Erase and Program Operations cannot be performed. VCC VCC VCC 0 1 1 1 0 0 1 0 1 No Yes No VCC 1 1 0 Yes VCC 1 1 1 No VIL x x x No Figure 3-2. Sector Locking State Diagram UNLOCKED 60h/ D0h [000] 60 h/2 Fh LOCKED 60h/01h [001] WP = VIL = 0 60h/ 2Fh Power-Up/Reset Default [011] Hardlocked 60h/D0h [110] 60h/ 01h [111] Hardlocked is disabled by WP = VIH WP = VIH = 1 60h/ D0h [100] 60h/ 2Fh 60h/ 2Fh Power-Up/Reset Default 60h/ 01h [101] 60h/D0h = Unlock Command 60h/01h = Softlock Command 60h/2Fh = Hardlock Command Note: 1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP and the two bits of the sector-lock status D[1:0]. 8 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 3.12.3 Sector Protection Detection A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode a read from the I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked. Table 3-3. I/O1 0 0 1 1 Sector Protection Status I/O0 0 1 0 1 Sector Protection Status Sector Not Locked Softlock Enabled Hardlock Enabled Both Hardlock and Softlock Enabled 3.13 Read Status Register The status register indicates the status of device operations and the success/failure of that operation. The Read Status Register command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the memory, issue a Read command. The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H when a Read Status Register command is issued. The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE (whichever occurs last), which prevents possible bus errors that might occur if status register contents change while being read. CE or OE must be toggled with each subsequent status read, or the status register will not indicate completion of a Program or Erase operation. When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the preferred operation (see Table 3-4). 9 3464C-FLASH-2/05 3.14 Read Status Register In The Burst Mode The waveform below shows a status register read during a program operation. The two-bus cycle command for a program operation is given followed by a read status register command. Following the read status register command, the AVD signal is pulsed low to latch the valid address at point A. With the OE signal pulsed low and for the specified clock latency of three, the status register output is valid within 13 ns from clock edge B. The same status register data is output on successive clock edges. To update the status register output, the AVD signal needs to be pulsed low and the next data is available after a clock latency of three. The status register output is also available after the chosen clock latency during an erase operation. Figure 3-3. Read Status Register in the Burst Mode A CLK CE B OE AVD WE A0 - A21 XX ADDRESS I/O0 - I/O15 40H/10H DATA 70H 00H 80H WAIT (1) Note: 1. The WAIT signal is for a burst configuration setting of B10 and B8 = 0. 10 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) Table 3-4. WSMS 7 Status Register Bit Definition ESS 6 ES 5 PRS 4 VPPS 3 PSS 2 Notes SLS 1 PLS 0 SR7 WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR6 = ERASE SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR5 = ERASE STATUS (ES) 1 = Error in Sector Erase 0 = Successful Sector Erase SR4 = PROGRAM STATUS (PRS) 1 = Error in Programming 0 = Successful Programming SR3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR1 = SECTOR LOCK STATUS 1 = Prog/Erase attempted on a locked sector; Operation aborted. 0 = No operation to locked sectors SR0 = Plane Status (PLS) Note: Check Write State Machine bit first to determine Word Program or Sector Erase completion, before checking program or erase status bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1" - ESS bit remains set to "1" until an Erase Resume command is issued. When this bit is set to "1", WSM has applied the max number of erase pulses to the sector and is still unable to verify successful sector erasure. When this bit is set to "1", WSM has attempted but failed to program a word The VPP status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP is also checked before the operation is verified by the WSM. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to "1". PSS bit remains set to "1" until a Program Resume command is issued. If a Program or Erase operation is attempted to one of the locked sectors, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. Indicates program or erase status of the addressed plane. 1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set. Table 3-5. WSMS (SR7) 0 0 1 Status Register Device WSMS and Write Status Definition PLS (SR0) 0 1 x Description The addressed plane is performing a program/erase operation. A plane other than the one currently addressed is performing a program/erase operation. No program/erase operation is in progress in any plane. Erase and Program suspend bits (SR6, SR2) indicate whether other planes are suspended. 11 3464C-FLASH-2/05 3.15 Erase Suspend/erase Resume The Erase Suspend command allows the system to interrupt a sector erase or plane erase operation. The erase suspend command does not work with the Chip Erase feature. Using the erase suspend command to suspend a sector erase operation, the system can program or read data from a different sector within the same plane. Since this device is organized into four planes, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in another plane. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address. Read, Read Status Register, Product ID Entry, Clear Status Register, Program, Program Suspend, Erase Resume, Sector Softlock/Hardlock, Sector Unlock are valid commands during an erase suspend. 3.16 Program Suspend/program Resume The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 s to suspend the programming operation. After the programming operation has been suspended, the system can then read from any other word within the device. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. Read, Read Status Register, Product ID Entry, Program Resume are valid commands during a Program Suspend. 3.17 128-bit Protection Register The AT49SN6416(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the two-bus cycle Program Protection Register command must be used as shown in the "Command Definition Table" on page 19. To lock out block B, the two-bus cycle lock protection register command must be used as shown in the "Command Definition Table". Data bit D1 must be zero during the second bus cycle. All other data bits during the second bus cycle are don't cares. To determine whether block B is locked out, the status of sector B command is given. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the "Protection Register Addressing Table" on page 20 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not or reading the protection register, the Read command must be given to return to the read mode. 12 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 3.18 Common Flash Interface (CFI) CFI is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to any address. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in "Common Flash Interface Definition Table" on page 37. To return to the read mode, the read command should be issued. 3.19 Hardware Data Protection Hardware features protect against inadvertent programs to the AT49SN6416(T) in the following ways: (a) VCC sense: if VCC is below 1.2V (typical), the device is reset and the program and erase functions are inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. (e) VPP is less than VILPP. 3.20 Input Levels While operating with a 1.65V to 1.95V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 2.5V without adversely affecting the operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V. 3.21 Output Levels For the AT49SN6416(T), output high levels are equal to VCCQ - 0.1V (not VCC). VCCQ must be regulated between 1.65V - 2.25V. 13 3464C-FLASH-2/05 3.22 Word Program Flowchart Start 3.23 Word Program Procedure Command Program Setup Data Comments Data = 40 Addr = Location to program Data = Data to program Addr = Location to program Status register data: Toggle CE or OE to update status register Check SR7 1 = WSM Ready 0 = WSM Busy Bus Operation Write Write 40, Word Address (Setup) Write Write Data, Word Address Read Status Register No (Confirm) Read Program Suspend Loop None Idle Yes None SR7 = 1 0 Suspend? Full Status Check (If Desired) Repeat for subsequent Word Program operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to set to the Read state. Program Complete 3.24 Full Status Check Flowchart Read Status Register 3.25 Full Status Check Procedure Command None None Comments Check SR3: 1 = VPP Error Check SR4: 1 = Data Program Error Check SR1: 1 = Sector locked; operation aborted Bus Operation Idle SR3 = 0 1 VP P Range Error Idle SR4 = 0 1 Program Error Idle None SR1 = 0 1 Device Protect Error SR3 MUST be cleared before the Write State Machine allows further program attempts. If an error is detected, clear the status register before continuing operations - only the Clear Status Register command clears the status register error bits. Program Successful 14 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 3.26 Program Suspend/Resume Flowchart Start 3.27 Program Suspend/Resume Procedure Command Program Suspend Read Status Comments Data = B0 Addr = Sector address to Suspend (SA) Data = 70 Addr = Any address within the Same Plane Status register data: Toggle CE or OE to update status register Addr = Any address Check SR7 1 = WSM Ready 0 = WSM Busy Check SR2 1 = Program suspended 0 = Program completed Data = FF Addr = Any address within the Suspended Plane Read data from any sector in the memory other than the one being programmed Data = D0 Addr = Any address Bus Operation (Program Suspend) Write B0 Any Address Write Write 70 Any Address (Read Status) within the Same Plane Read Status Register Write Read SR7 = 1 0 0 None SR2 = 1 Program Completed Idle None Write FF Suspend Plane (Read Array) Idle None Read Data Write FF (Read Array) Write Read Array Done Reading Yes No Read Data Read (Program Resume) None Program Resume Write D0 Any Address Write Program Resumed If the Suspend Plane was placed in Read mode: Read Status Return Plane to Status mode: Data = 70 Addr = Any address within the Same Plane Write 70H Any Address within the Same Plane (Read Status) Write 15 3464C-FLASH-2/05 3.28 Erase Suspend/Resume Flowchart Start 3.29 Erase Suspend/Resume Procedure Command Erase Suspend Read Status Comments Data = B0 Addr = Any address within the Same Plane Data = 70 Addr = Any address Status register data: Toggle CE or OE to update status register Addr = Any address within the Same Plane Check SR7 1 = WSM Ready 0 = WSM Busy Check SR6 1 = Erase suspended 0 = Erase completed Data = FF or 40 Addr = Any address Read or program data from/to sector other than the one being erased Data = D0 Addr = Any address Bus Operation (Erase Suspend) Write B0, Any Address Write Write 70, Any Address Read Status Register (Read Status) Write SR7 = 1 0 Read None SR6 = 1 0 Erase Completed Idle None Read or Program? Read No Program Loop Idle None Done? Yes (Erase Resume) Write Read or Write Write Read or Program None Program Resume Write D0, Any Address Erase Resumed Write FF (Read Array) Read Array Data Write 70H Any Address within the Same Plane (Read Status) If the Suspended Plane was placed in Read mode or a Program loop: Read Status Return Plane to Status mode: Data = 70 Addr = Any address within the Same Plane Write 16 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 3.30 Sector Erase Flowchart Start 3.31 Sector Erase Procedure Command Sector Erase Setup Erase Confirm None Comments Data = 20 Addr = Sector to be erased (SA) Data = D0 Addr = Sector to be erased (SA) Status register data: Toggle CE or OE to update status register data Check SR7 1 = WSMS Ready 0 = WSMS Busy Bus Operation (Sector Erase) Write 20, Sector Address Write Write D0, (Erase Confirm) Sector Address Read Status Register No Write Suspend Erase Loop Read SR7 = 1 0 Suspend Erase Yes Idle None Full Erase Status Check (If Desired) Sector Erase Complete Repeat for subsequent sector erasures. Full status register check can be done after each sector erase, or after a sequence of sector erasures. Write FF after the last operation to enter read mode. 3.32 Full Erase Status Check Flowchart Read Status Register 1 3.33 Full Erase Status Check Procedure Command None Comments Check SR3: 1 = VPP Range Error Check SR4, SR5: Both 1 = Command Sequence Error Check SR5: 1 = Sector Erase Error Check SR1: 1 = Attempted erase of locked sector; erase aborted. Bus Operation VP P Range Error Command Sequence Error SR3 = 0 SR4, SR5= Idle 1,1 Idle None 0 SR5 = 0 1 Sector Erase Error Idle None SR1 = 0 1 Sector Locked Error Idle None Sector Erase Successful SR1, SR3 must be cleared before the Write State Machine allows further erase attempts. Only the Clear Status Register command clears SR1, SR3, SR4, SR5. If an error is detected, clear the status register before attempting an erase retry or other error recovery. 17 3464C-FLASH-2/05 3.34 Protection Register Programming Flowchart Start 3.35 Protection Register Programming Procedure Command Program PR Setup Protection Program None Comments Data = C0 Addr = First Location to Program Data = Data to Program Addr = Location to Program Status register data: Toggle CE or OE to update status register data Check SR7 1 = WSMS Ready 0 = WSMS Busy Bus Operation (Program Setup) Write C0, PR Address Write Write Write PR Address & Data (Confirm Data) Read Status Register Read SR7 = 1 0 Idle None Full Status Check (If Desired) Program Complete Program Protection Register operation addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to return to the Read mode. 3.36 Full Status Check Flowchart Read Status Register Data 3.37 Full Status Check Procedure Command None None Comments Check SR1, SR3, SR4: 0,1,1 = VPP Range Error Check SR1, SR3, SR4: 0,0,1 = Programming Error Check SR1, SR3, SR4: 1, 0,1 = Sector locked; operation aborted Bus Operation 1, 1 Idle VP P Range Error SR3, SR4 = 0 Idle 0, 1 SR1, SR4 = Program Error Idle 0 None SR1, SR4 = 0 1, 1 Register Locked; Program Aborted Program Successful SR3 must be cleared before the Write State Machine allows further program attempts. Only the Clear Status Register command clears SR1, SR3, SR4. If an error is detected, clear the status register before attempting a program retry or other error recovery. 18 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 4. Command Definition Table Command Sequence Read Chip Erase Plane Erase Sector Erase Word Program Dual Word Program (10) Bus Cycles 1 2 2 2 2 3 1 1 1 2 2 2 2 1 2 2 2 2 2 1 1st Bus Cycle Addr PA (2) 2nd Bus Cycle Data FF 21 22 20 40/10 E0 B0 D0 90 60 60 60 70 50 C0 XX(9) XXXX 80 XXXX 80 (13) (13) 3rd Bus Cycle Data Addr Data Addr XX XX SA (3) (4) Addr Addr SA (3) (4) D0 D0 D0 DIN DIN0 Addr1 DIN1 Addr Addr Addr0 XX PA (2) (2) (3) (3) (3) Addr0 Erase/Program Suspend Erase/Program Resume Product ID Entry Sector Softlock Sector Hardlock Sector Unlock Read Status Register Clear Status Register Program Protection Register Lock Protection Register - Sector B Status of Sector B Protection Program Burst Configuration Register Read Burst Configuration Register CFI Query Notes: (11)(12) PA SA SA SA(3) SA SA (3) (3) 01 2F D0 DOUT(5) DIN FFFD DOUT(6) 03 DOUT SA PA (2) XX XX XX (9) (13) (13) XXXX 80 C0 90 60 90 98 XXXX 80 (2) Addr(7) PA Addr(7) XXX (8) XX 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don't care. The ADDRESS FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A21 through A8 are don't care. 2. PA is the plane address (A21 - A20). Any address within a plane can be used. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 23 - 26 for details). 4. The first bus cycle address should be the same as the word address to be programmed. 5. The status register bits are output on I/O7 - I/O0. 6. If data bit D1 is "0", sector B is locked. If data bit D1 is "1", sector B can be reprogrammed. 7. See "Burst Configuration Register Table" on page 21. Bits B15 - B0 of the burst configuration register determine A15 - A0. Addresses A16 - A21 can select any plane. For the AT49SN6416T: 8. For the AT49SN6416: xxx = 000005 Burst Configuration Register Data from Plane A xxx = 100005 Burst Configuration Register Data from Plane B xxx = 200005 Burst Configuration Register Data from Plane C xxx = 300005 Burst Configuration Register Data from Plane D xxx = 000005 Burst Configuration Register Data from Plane D xxx = 100005 Burst Configuration Register Data from Plane C xxx = 200005 Burst Configuration Register Data from Plane B xxx = 300005 Burst Configuration Register Data from Plane A 9. Any address within the user programmable protection register region. Please see "Protection Register Addressing Table" on page 20. 10. This fast programming option enables the user to program two words in parallel only when VPP = 10V. The addresses, Addr0 and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used during manufacturing purposes only. 11. During the second bus sycle, the manufacturer code is read from address PA+00000H, the device code is read from address PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H (AT49SN6416) or addresses 3F8081H - 3F8088H (AT49SN6416T). 12. The plane address should be the same during the first and second bus cycle. 13. For the AT49SN6416, xxxx = 0000H. For the AT49SN6416T, xxxx = 3F80H. 19 3464C-FLASH-2/05 5. Absolute Maximum Ratings* Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages Except VPP (Including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V VPP Input Voltage with Respect to Ground ......................................... 0V to 10.0V All Output Voltages with Respect to Ground ...........................-0.6V to VCCQ + 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6. Protection Register Addressing Table Word 0 1 2 3 4 5 6 7 Notes: Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0 1. For the AT49SN6416, all address lines not specified in the above table, A21 - A8, must be 0 when accessing the Protection Register. 2. For the AT49SN6416T, all address lines not specified in the above table, A21 - A8, must be 3F80H when accessing the Protection Register. 20 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 7. Burst Configuration Register Table B15 Program (AT49SN6416) B15 Program (AT49SN6416T) B15 Read B14 010 011 B13 - B11:(2) 100 101 110(1) B10 B9 B8 B7 B6 B5 - B4 B3 0 1(1)(3) 0 1(1) 0 1(1) 1 0 1(1) 00 0 1(1) 001 B2 - B0 010 011 111(1) (1) (1) 0 1(1) 1 0(1) 0 1 Synchronous Burst Reads Enabled Asynchronous BurstReads Enabled Synchronous Burst Reads Enabled Asynchronous BurstReads Enabled Synchronous Burst Reads Enabled Asynchronous BurstReads Enabled Reserved for future use Clock Latency of Two Clock Latency of Three Clock Latency of Four Clock Latency of Five Clock Latency of Six WAIT Signal is Asserted Low WAIT Signal is Asserted High Hold Data for One Clock Hold Data for Two Clocks WAIT Asserted during Clock Cycle in which Data is Valid WAIT Asserted One Clock Cycle before Data is Valid Linear Burst Sequence Burst Starts and Data Output on Falling Clock Edge Burst Starts and Data Output on Rising Clock Edge Reserved for Future Use Reserved for future use Don't Wrap Accesses Within Burst Length set by B2 - B0 Four-word Burst Eight-word Burst Sixteen-word Burst Continuous Burst Notes: 1. Default State 2. Burst configuration setting of B13 - B11 = 010 (clock latency of two), B9 = 1 (hold data for two clock cycles) and B8 = 1 (WAIT asserted one clock cycle before data is valid) is not supported. 3. Data is not ready when WAIT is asserted. 8. Clock Latency versus Input Clock Frequency Minimum Clock Latency (Minimum Number of Clocks Following Address Latch) 5, 6 4 2, 3 Input Clock Frequency 66 MHz 61 MHz 40 MHz Figure 8-1. Output Configuration CLK 1 CLK Data Hold (B9 = 0) 2 CLK Data Hold (B9 = 1) I/00 - I/015 VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT I/00 - I/015 21 3464C-FLASH-2/05 9. Sequence and Burst Length Burst Addressing Sequence (Decimal) 4-word Burst Length B2 - B0 = 001 Linear 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 8-word Burst Length B2 - B0 = 010 Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-13-14 ... ... 16-word Burst Length B2 - B0 = 011 Linear 0-1-2...14-15 1-2-3...15-16 2-3-4...16-17 3-4-5...17-18 4-5-6...18-19 5-6-7...19-20 6-7-8...20-21 7-8-9...21-22 ... 14-15...28-29 15-16...29-30 Continuous Burst B2 - B0 = 111 Linear 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... 3-4-5-6-7-8-9... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20 15-16-17-18-19-20-21 Start Addr. (Decimal) 0 1 2 3 4 5 6 7 ... 14 15 Wrap B3 = 1 1 1 1 1 1 1 1 1 ... 1 1 22 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 10. Memory Organization - AT49SN6416 x16 Plane A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) 4K 4K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF Plane A A A B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 10. Memory Organization - AT49SN6416 (Continued) x16 Address Range (A21 - A0) E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 23 3464C-FLASH-2/05 10. Memory Organization - AT49SN6416 (Continued) x16 Plane C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C Sector SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 288000 - 28FFFF 290000 - 297FFF 298000 - 29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF 2D0000 - 2D7FFF 2D8000 - 2DFFFF 2E0000 - 2E7FFF 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 10. Memory Organization - AT49SN6416 (Continued) x16 Plane D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D Sector SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF 340000 - 347FFF 348000 - 34FFFF 350000 - 357FFF 358000 - 35FFFF 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF 380000 - 387FFF 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3FFFFF 24 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 11. Memory Organization - AT49SN6416T x16 Plane D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D C C C C Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF Plane C C C C C C C C C C C C C C C C C C C C C C C C C C C C B B B B B B B B Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 11. Memory Organization - AT49SN6416T (Continued) x16 Address Range (A21 - A0) 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF 25 3464C-FLASH-2/05 11. Memory Organization - AT49SN6416T (Continued) x16 Plane B B B B B B B B B B B B B B B B B B B B B B B B A A A A A A A A A Sector SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 288000 - 28FFFF 290000 - 297FFF 298000 -29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF 2D0000 - 2D7FFF 2D8000 - 2DFFFF 2E0000 - 2E7FFF 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF 340000 - 347FFF 11. Memory Organization - AT49SN6416T (Continued) x16 Plane A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Sector SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 4K 4K Address Range (A21 - A0) 348000 - 34FFFF 350000 - 357FFF 358000 - 35FFFF 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF 380000 - 387FFF 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3F8FFF 3F9000 - 3F9FFF 3FA000 - 3FAFFF 3FB000 - 3FBFFF 3FC000 - 3FCFFF 3FD000 - 3FDFFF 3FE000 - 3FEFFF 3FF000 - 3FFFFF 26 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 12. DC and AC Operating Range AT49SN6416(T)-70 Operating Temperature (Case) VCC Power Supply Industrial -40C - 85C 1.65V - 1.95V 13. Operating Modes Mode Read Burst Read Program/Erase (3) CE VIL VIL VIL VIH X OE VIL VIL VIH X(1) X VIL X VIH X WE VIH VIH VIL X VIH X X X X RESET VIH VIH VIH VIH VIH VIH X VIH VIL VIH VPP(4) X X VIHPP(5) X X X VILPP(6) X X Ai Ai Ai Ai X I/O DOUT DOUT DIN High Z Standby/Program Inhibit Program Inhibit X X Output Disable Reset Product Identification Software Notes: 1. 2. 3. 4. 5. 6. X X High Z X A0 = VIL, A1 - A21 = VIL A0 = VIH, A1 - A21 = VIL High Z Manufacturer Code(3) Device Code(3) X can be VIL or VIH. Refer to AC programming waveforms. Manufacturer Code: 001FH; Device Code: 00DE - AT49SN6416; 00D8H - AT49SN6416T. The VPP pin can be tied to VCC. For faster program operations, VPP can be set to 9.5V 0.5V. VIHPP (min) = 0.9V. VILPP (max) = 0.4V. 27 3464C-FLASH-2/05 14. DC Characteristics Symbol ILI ILO ISB1 ICC(1) ICCRE ICCRW VIL VIH VOL Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Current VCC Read While Erase Current VCC Read While Write Current Input Low Voltage Input High Voltage Output Low Voltage IOL = 100 A IOL = 2.1 mA IOH = -100 A IOH = -400 A VCCQ - 0.1 1.4 VCCQ - 0.2 0.1 0.25 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCCQ - 0.3V to VCC f = 66 MHz; IOUT = 0 mA f = 66 MHz; IOUT = 0 mA f = 66 MHz; IOUT = 0 mA Min Max 1 1 35 30 50 50 0.4 Units A A A mA mA mA V V V VOH Output High Voltage V Note: 1. In the erase mode, ICC is 30 mA. 15. Input Test Waveforms and Measurement Level 1.4V AC DRIVING LEVELS 0.4V 0.9V AC MEASUREMENT LEVEL tR, tF < 5 ns 16. Output Test Load VCCQ 1.8K OUTPUT PIN 1.3K 30 pF 17. Pin Capacitance f = 1 MHz, T = 25C(1) Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 1. This parameter is characterized and is not 100% tested. 28 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 18. AC Asynchronous Read Timing Characteristics Symbol tACC1 tACC2 tCE tOE tAHAV tAVLP tAVHP tAAV tDF tOH tRO Parameter Access, AVD To Data Valid Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid Address Hold from AVD AVD Low Pulse Width AVD High Pulse Width Address Valid to AVD CE, OE High to Data Float Output Hold from OE, CE or Address, Whichever Occurred First RESET to Output Delay 0 150 9 10 10 10 25 Min Max 70 70 70 20 Units ns ns ns ns ns ns ns ns ns ns ns 19. AVD Pulsed Asynchronous Read Cycle Waveform(1)(2) tCE CE tDF I/O0-I/O15 tACC2 A2 -A21 tAAV tAHAV tACC2 A0 -A1 tAAV tAVHP tAVLP tACC1 OE tRO RESET tOE tAHAV DATA VALID tDF AVD (1) Notes: 1. After the high-to-low transition on AVD, AVD may remain low as long as the address is stable. 2. CLK may be static high or static low. 20. Asynchronous Read Cycle Waveform(1)(2)(3)(4) tRC A0 - A21 ADDRESS VALID CE tCE OE tOE tDF tACC2 tRO HIGH Z OUTPUT VALID tOH RESET I/O0 - I/O15 Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. AVD and CLK should be tied low. 29 3464C-FLASH-2/05 21. AC Asynchronous Read Timing Characteristics Symbol tACC1 tACC2 tCE tOE tAHAV tAVLP tAVHP tAAV tDF tRO tPAA Parameter Access, AVD To Data Valid Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid Address Hold from AVD AVD Low Pulse Width AVD High Pulse Width Address Valid to AVD CE, OE High to Data Float RESET to Output Delay Page Address Access Time 9 10 10 10 25 150 20 Min Max 70 70 70 20 Units ns ns ns ns ns ns ns ns ns ns ns 22. Page Read Cycle Waveform 1(1) tCE CE tDF I/O0-I/O15 tACC2 A2 -A21 tAAV tAHAV tACC2 A0 -A1 tAAV tAVHP tAVLP tACC1 OE tRO RESET tOE tAHAV tPAA DATA VALID tDF AVD (1) Note: 1. After the high-to-low transition on AVD, AVD may remain low as long as the page address is stable. 23. Page Read Cycle Waveform 2(1) tCE CE tDF I/O0-I/O15 tACC2 A2 -A21 tPAA tACC2 A0 -A1 DATA VALID tDF AVD (1) VIL tOE tRO RESET OE Note: 1. AVD may remain low as long as the page address is stable. 30 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 24. AC Burst Read Timing Characteristics Symbol tCLK tCKH tCKL tCKRT tCKFT tACK tAVCK tCECK tCKAV tQHCK tAHCK tCKRY tCESAV tAAV tAHAV tCKQV tCEQZ Parameter CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time Address Valid to Clock AVD Low to Clock CE Low to Clock Clock to AVD High Output Hold from Clock Address Hold from Clock Clock to WAIT Delay CE Setup to AVD Address Valid to AVD Address Hold From AVD CLK to Data Delay CE High to Output High-Z 10 10 9 13 10 7 7 7 3 3 8 13 Min 15 4 4 3.5 3.5 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25. Burst Read Cycle Waveform tCLK CLK tAHCK tCECK CE tCE tCESAV tAVCK AVD (2) tCKH ... ... tCKL ... tACK tCKAV tAAV tAHAV tQHCK D3 D4 ... D14 tCKQV tCEQZ I/O0-I/O15 D15 D16 D17 A0-A21 OE tCKRY WAIT (1) tCKRY Notes: 1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid line) shown is for a burst configuration setting of B10 = 1 and B8 = 0. 2. After the high-to-low transition on AVD, AVD may remain low. 31 3464C-FLASH-2/05 26. Burst Read Waveform (Clock Latency of 4) A CLK B C D E F G CE AVD OE A0-A21 VALID I/O0-I/O15 D11 D12 D13 D14 D15 D16 D17 D18 WAIT (1) HIGH Z HIGH Z Note: 1. Dashed line reflects a B10 and B8 setting of 0 in the configuration register. Solid line reflects a B10 setting of 0 and B8 setting of 1 in the configuration register. 27. Hold Data for 2 Clock Cycles Read Waveform (Clock Latency of 4) AVD CLK CE OE A0-A21 A9 I/O0-I/O15 D9 D10 D11 D12 D13 D14 D15 D16 WAIT(1) Note: 1. The Dashed line reflects a burst configuration register setting of B10 and B8 = 0, B9 = 1. Solid line reflects a burst configuration register setting of B10 = 0, B8 and B9 = 1. 32 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 28. Four-word Burst Read Waveform (Clock Latency of 4) A CLK B C CE AVD OE A0-A21 VALID I/O0-I/O15 (1) D0 HIGH Z D1 D2 D3 HIGH Z WAIT Note: 1. The WAIT signal shown is for a burst configuration register of B10 and B8 = 1. 29. Burst Suspend Waveform tCLK CLK (2) tCKH tCKL ... tAHCK tCECK CE tCE tCEAV tAVCK AVD tACK tCKAV tAAV I/O0-I/O15 tAHAV tQHCK D0 D1 D1 D2 tCKQV tCEQZ A0-A21 tDF OE tOE WAIT (2) Notes: 1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid line) shown is for a burst configuration setting of B10 = 1 and B8 = 0. 2. During Burst Suspend, CLK signal can be held low or high. 33 3464C-FLASH-2/05 30. AC Word Load Characteristics 1 Symbol tAAV tAHAV tAVLP tDS tDH tCESAV tWP tWPH tWEAV tCEAV Parameter Address Valid to AVD High Address Hold Time from AVD High AVD Low Pulse Width Data Setup Time Data Hold Time CE Setup to AVD CE or WE Low Pulse Width CE or WE High Pulse Width WE High Time to AVD Low CE High Time to AVD Low Min 10 9 10 50 0 10 35 25 25 25 Max Units ns ns ns ns ns ns ns ns ns ns 31. AC Word Load Waveforms 1 31.1 WE Controlled(1) CE I/O0-I/O15 DATA VALID A0 -A21 tAAV tAHAV AVD tAVLP tDS tDH tWEAV tWP WE Note: 1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle. 31.2 CE Controlled(1) WE I/O0-I/O15 DATA VALID A0 -A21 tAAV tAHAV AVD tAVLP tCESAV CE tWP tDS tDH tCEAV Note: 1. After the high-to-low transition on AVD, AVD may remain low as long as the CLK input does not toggle. 34 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 32. AC Word Load Characteristics 2 Symbol tAS tAH tDS tDH tWP tWPH Parameter Address Setup Time to WE and CE High Address Hold Time Data Setup Time Data Hold Time CE or WE Low Pulse Width CE or WE High Pulse Width Min 50 0 50 0 35 25 Max Units ns ns ns ns ns ns 33. AC Word Load Waveforms 2 33.1 WE Controlled(1) CE I/O0 - I/O15 DATA VALID A0 - A21 WE AVD VIL Note: 1. The CLK input should not toggle. 33.2 CE Controlled(1) WE I/O0 - I/O15 DATA VALID A0 - A21 CE AVD VIL Note: 1. The CLK input should not toggle. 35 3464C-FLASH-2/05 34. Program Cycle Characteristics Symbol tBP tWC tSEC1 tSEC2 tES tPS tERES Parameter Word Programming Time Write Cycle Time Sector Erase Cycle Time (4K word sectors) Sector Erase Cycle Time (32K word sectors) Erase Suspend Time Program Suspend Time Delay between Erase Resume and Erase Suspend 500 200 700 15 10 ms ms s s s Min Typ 22 Max Units s 35. Program Cycle Waveforms PROGRAM CYCLE OE CE tWP tBP WE tAS tWPH tDH tAH (1) A0 - A21 XX ADDRESS tWC tDS INPUT DATA I/O0 - I/O15 Note 3 AVD VIL 36. Sector, Plane or Chip Erase Cycle Waveforms OE (2) CE tWP WE tAS tWPH tDH tAH (1) A0 - A21 XX Note 4 tWC tDS tSEC1/2 D0 I/O0 - I/O15 Note 5 WORD 0 WORD 1 AVD VIL Notes: 1. 2. 3. 4. Any address can be used to load data. OE must be high only when WE and CE are both low. The data can be 40H or 10H. For chip erase, any address can be used. For plane erase or sector erase, the address depends on what plane or sector is to be erased. 5. For chip erase, the data should be 21H, for plane erase, the data should be 22H, and for sector erase, the data should be 20H. 36 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 37. Common Flash Interface Definition Table Address 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h AT49SN6416T 0051h 0052h 0059h 0003h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0016h 0019h 00B5h 00C5h 0004h 0000h 0009h 0010h 0004h 0000h 0003h 0003h 0017h 0001h 0000h 0000h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h AT49SN6416 0051h 0052h 0059h 0003h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0016h 0019h 0009h 000Ah 0004h 0000h 0009h 0010h 0004h 0000h 0003h 0003h 0017h 0001h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h Typ block erase - 500 ms Typ chip erase - 64,300 ms Max word write/typ time n/a Max block erase/typ block erase Max chip erase/ typ chip erase Device size x16 device x16 device Multiple byte write not supported Multiple byte write not supported 2 regions, x = 2 64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom) 64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom) 64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom) 64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom) 8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom) 8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom) 8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom) 8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom) VCC min write/erase VCC max write/erase VPP min voltage VPP max voltage Typ word write - 16 s Comments "Q" "R" "Y" 37 3464C-FLASH-2/05 37. Common Flash Interface Definition Table (Continued) Address AT49SN6416T AT49SN6416 Comments VENDOR SPECIFIC EXTENDED QUERY 41h 42h 43h 44h 45h 0050h 0052h 0049h 0031h 0030h 0050h 0052h 0049h 0031h 0030h "P" "R" "I" Major version number, ASCII Minor version number, ASCII Bit 0 - chip erase supported, 0 - no, 1 - yes Bit 1 - erase suspend supported, 0 - no, 1 - yes Bit 2 - program suspend supported, 0 - no, 1 - yes Bit 3 - simultaneous operations supported, 0 - no, 1 - yes Bit 4 - burst mode read supported, 0 - no, 1 - yes Bit 5 - page mode read supported, 0 - no, 1 - yes Bit 6 - queued erase supported, 0 - no, 1 - yes Bit 7 - protection bits supported, 0 - no, 1 - yes Bit 0 - top ("0") or bottom ("1") boot block device Undefined bits are "0" Bit 0 - 4 word linear burst with wrap around, 0 - no, 1 - yes Bit 1 - 8 word linear burst with wrap around, 0 - no, 1 - yes Bit 2 - 16 word linear burst with wrap around, 0 - no, 1 - yes Bit 3 - continuous burst, 0 - no, 1 - yes Undefined bits are "0" Bit 0 - 4 word page, 0 - no, 1 - yes Bit 1 - 8 word page, 0 - no, 1 - yes Undefined bits are "0" Location of protection register lock byte, the section's first byte # of bytes in the factory prog section of prot register - 2*n # of bytes in the user prog section of prot register - 2*n 46h 00BFh 00BFh 47h 0000h 0001h 48h 000Fh 000Fh 49h 4Ah 4Bh 4Ch 0001h 0080h 0003h 0003h 0001h 0080h 0003h 0003h 38 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 38. Ordering Information 38.1 tACC (ns) 70 70 Standard Package ICC (mA) Active 30 30 Standby 0.035 0.035 Ordering Code AT49SN6416-70CI AT49SN6416T-70CI Package 56C2 56C2 Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C) Package Type 56C2 56-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 39 3464C-FLASH-2/05 39. Packaging Information 39.1 56C2 - CBGA D 0.12 C C Seating Plane E Side View Top View A A1 0.875 mm Ref 87 6 D1 5 4 3 21 A B C D E F G E1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A MIN - 0.21 6.90 NOM - - 7.00 5.25 TYP 9.90 10.00 4.50 TYP 0.75 TYP 0.35 TYP 10.10 MAX 1.00 - 7.10 NOTE e 2.75 mm Ref e Ob A1 D D1 Bottom View E E1 e Ob 1/9/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 56C2, 56-ball (8 x 7 Array), 7 x 10 x 1.0 mm Body, 0.75 mm Ball Pitch Ceramic Ball Grid Array Package (CBGA) DRAWING NO. 56C2 REV. A R 40 AT49SN6416(T) 3464C-FLASH-2/05 AT49SN6416(T) 40. Revision History Revision No. Revision A - March 2004 History * * Revision B - April 2004 Initial Release Timing diagrams on pages 31, 32, and 33 were changed such that the default state is now shown as a solid line (shown as dashed line before). Added a note in the "Burst Configuration Register Table" regarding the usee of Clock Latency of Two. Wrap option removed on pages 3, 21 and 22. Converted datasheet to New Template. Removed "Preliminary" from the datasheet. Changed the VPP value to 9.5V + 0.5V in the text, table on page 19, and CFI table. VPP text also changed to show that a high voltage on VPP improves only the programming time. Changed the ISB1 spec to 35 A. Modified note 11 and added note 12 on page 19. Modified note 1 and added note 2 on page 20. Modified the B15 section in the "Burst Configuration Register Table" on page 21 * * * * * Revision C - January 2005 * * * * 41 3464C-FLASH-2/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) Atmel Corporation 2005. All rights reserved. Atmel(R), logo and combinations thereof, and others, are registered trademarks, and Everywhere You AreSM and others are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 3464C-FLASH-2/05 xM |
Price & Availability of AT49SN6416-70CI
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |